RISC-V: A Technical Critique of Its ISA Design Choices
Original: RISC-V: They Should Have Known Better
Why This Matters
Technical ISA critique from an embedded engineer highlights real fragmentation and design tradeoff concerns as RISC-V adoption accelerates across the industry.
Embedded systems engineer Dmitry Grinberg published a detailed technical critique of RISC-V's ISA, arguing that its 'everything for everyone' design philosophy results in poor tradeoffs for both high-performance and low-cost microcontroller use cases, citing encoding inefficiencies and missing baseline features.
Dmitry Grinberg, an embedded systems engineer, published a comprehensive critique of RISC-V's instruction set architecture (ISA). His central argument is that RISC-V's attempt to serve all markets—from supercomputers to tiny microcontrollers—is fundamentally flawed, as the design requirements for these use cases are 'diametrically opposed.' For cheap embedded microcontrollers, Grinberg argues the key requirements are low interrupt latency, small die size, and high code density. He contends that even the minimal RV32EC profile falls short because proper interrupt handling requires the Zicsr extension for the mscratch/sscratch registers, making the effective baseline larger than advertised. He draws an unfavorable comparison to MIPS, which reserved dedicated registers ($k0, $k1) for interrupt handling without extra extensions. Grinberg further criticizes RISC-V's modular 'optionality' as creating fragmentation, its instruction encoding as inefficient, and questions whether proposed fixes adequately address the core architectural issues. He does acknowledge that RISC-V will likely dominate the cheap single-use microcontroller space, but attributes this to its improvement over the aging 8051 standard rather than any inherent ISA quality. The post is intended as a consolidated reference for technical debate.