RISC-V CPU baked into Qwen3.5's weights
Original: Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5
Why This Matters
Shows LLM internals can host deterministic compute without any external tooling.
Developer Divyansh Agrawal embedded a functional, deterministic RISC-V CPU into Qwen 3.5 4B's weights, using the model's own Gated DeltaNet layers as RAM. It runs arithmetic, C, and MicroPython code with no external tools or sandboxing.
Dubbed Qwenputer, the project modifies a stock Qwen 3.5 4B model by compiling a RISC-V CPU directly into its weights—no plugins, no tool calls, no external runtime. The CPU executes entirely within the model's forward passes, and its RAM is the model's Gated DeltaNet (GDN) attention layers, which handle 3 out of every 4 attention layers in Qwen 3.5.
Agrawal found that by setting the GDN gate to 1 (no forgetting), write strength beta to 1 (full overwrite), and using one-hot key encoding, each write targets exactly one row of the state matrix—functionally identical to addressed RAM. Reads via one-hot queries retrieve exact values. This makes GDN state cheaper than standard attention KV cache, which grows with context length; GDN state stays fixed.
The theoretical underpinning traces back to Schlag et al.'s 2021 ICML paper showing linear attention with the delta rule acts as associative memory. Agrawal's contribution is making it exact, addressable, and stable enough to run a full CPU inside a production model. Two follow-up posts explore hiding reasoning in RNN state to evade chain-of-thought monitoring, and using compiled weights as tamper-proof monitoring tools. Code is on GitHub; the model is on Hugging Face and ModelScope.