IBM Introduces World's First Sub-1 Nanometer Chip Technology
Original: IBM debuts sub-1 nanometer chip technology
Why This Matters
Represents major advancement in semiconductor manufacturing as industry faces physical limits of traditional scaling, enabling continued performance gains for AI and computing infrastructure.
IBM unveiled its first sub-1 nanometer chip technology on June 25, 2026, featuring a revolutionary 0.7 nm transistor architecture with nearly 100 billion transistors. The breakthrough uses IBM's new nanostack 3D chip design, delivering up to 50 percent more performance or 70 percent greater energy efficiency than IBM's 2 nm chips from 2021.
IBM announced the development of the world's first sub-1 nanometer (0.7 nm or 7 angstrom) chip technology, marking a significant semiconductor advancement as the industry approaches the physical limits of traditional chip scaling. The new chip packs nearly 100 billion transistors onto a fingernail-sized chip, approximately double the density of IBM's 2 nm chip unveiled in 2025.
The breakthrough is enabled by IBM's revolutionary nanostack architecture, a three-dimensional, nanosheet-based transistor design that vertically stacks and staggers transistors. This approach uses 3D sequential integration to maximize transistor density while allowing different material combinations in each stacked layer, optimizing individual transistor performance and power efficiency independently.
According to technical results, the sub-1 nm chip is projected to deliver up to 50 percent greater performance or 70 percent improved energy efficiency compared to IBM's 2 nm node chips. Jay Gambetta, Director of IBM Research and IBM Fellow, stated: "With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency."
The nanostack technology was experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering capability demonstration, and functional CMOS inverter operation. IBM researchers also demonstrated that nanostack architecture provides 40 percent scaling in SRAM. The technology supports applications including generative AI, cloud infrastructure, and next-generation electronic devices.