Assembly Hall of Shame: Slowest x86 Instructions
Original: Assembly Hall of Shame
Why This Matters
Reveals hardware latency boundaries useful for security research, fuzzing, and worst-case CPU behavior analysis.
GitHub user xoreaxeaxeax published 'Assembly Hall of Shame,' an open-source project that deliberately seeks the worst-performing single x86 CPU instructions. The current champion is fxrstor64, which loads 512-byte FPU/MMX/XMM state from a high-latency MMIO region while PCIe fabric traffic is saturated by competing cores.
The 'Assembly Hall of Shame' project, published on GitHub by xoreaxeaxeax, inverts typical instruction latency analysis by racing to find the absolute performance floor of individual x86 CPU instructions rather than optimizing for speed. The repository includes benchmarks and artifacts for dozens of instructions including rdrand, rdseed, wbinvd, fsin, fyl2x, rdmsr, wrmsr, cpuid, and many others. The current 'champion' for worst single-instruction performance is fxrstor64. The method involves using fxrstor64 to load 512 bytes of FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, while simultaneously saturating the PCIe root complex and endpoint with non-posted transactions via 'hammer' cores issuing tight 4-byte reads to a separate high-latency MMIO register. This forces CPU 0's fxrstor64 to queue behind all contending PCIe traffic, maximizing its latency. The project also documents split_lock, lock_hammer, and MMIO-based extremes. The repository is MIT-licensed and has 254 stars as of publication.